The 8N3PG10MBKI-062 is a very versatile programmable LVPECL synthesizer that can be used for OTN/SONET to Ethernet or 10 GB Ethernet to OTN/SONET rate conversions. The conversion rate is pin-selectable and one of the four rates is supported at a time. In the default configuration, an input clock of 100MHz is converted to 311.04MHz output.
 
The device uses IDT’s fourth generation FemtoClock NG technology to deliver low phase noise clocks combined with low power consumption.

特性

  • Fourth Generation FemtoClock® Next Generation (NG)
    technology
  • Footprint compatible with 5mm x 7mm differential oscillators
  • One differential LVPECL output pair
  • CLK, nCLK input pair can accept the following levels: HCSL,
    LVDS, LVPECL and LVHSTL
  • Output frequencies: 150MHz, 125MHz, 155.52MHz and
    311.04MHz
  • RMS phase jitter, 12kHz – 20MHz: 0.295ps (typical) @ 3.3V
  • Full 3.3V or 2.5V operating supply
  • -40°C to 85°C ambient operating temperature
  • Lead-free (RoHS 6) packaging

description文档

文档标题 language 类型 文档格式 文件大小 日期
star 8N3PG10MBKI-062 Datasheet 数据手册 PDF 714 KB
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-831 The Crystal Load curve 应用文档 PDF 395 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-838 Peak-to-Peak Jitter Calculations 应用文档 PDF 115 KB
AN-839 RMS Phase Jitter 应用文档 PDF 233 KB
AN-832 Timing Budget and Accuracy 应用文档 PDF 131 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-830 Quartz Crystal Drive Level 应用文档 PDF 143 KB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-802 Crystal-Measuring Oscillator Negative Resistance 应用文档 PDF 136 KB
AN-801 Crystal-High Drive Level 应用文档 PDF 202 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
AN-806 Power Supply Noise Rejection 应用文档 PDF 438 KB
AN-803 Crystal Timing Budget and Accuracy for Renesas Timing Clock Products 应用文档 PDF 108 KB
IDT Clock Generation Overview 概览 PDF 1.83 MB

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